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low capacitance, triple/quad spdt 15 v/+12 v i cmos? switches adg1233/ADG1234 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 1.5 pf off capacitance 0.5 pc charge injection 33 v supply range 120 on resistance fully specified at 15 v/+12 v 3 v logic-compatible inputs rail-to-rail operation break-before-make switching action 16-lead tssop, 20-lead tssop, and 4 mm 4 mm lfcsp typical power consumption (<0.03 w) applications audio and video routing automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems communication systems general description the adg1233 and ADG1234 are monolithic i cmos analog switches comprising three independently selectable single-pole, double throw spdt switches and four independently selectable spdt switches, respectively. all channels exhibit break-before-make switching action preventing momentary shorting when switching channels. an en input on the adg1233 and ADG1234 is used to enable or disable the device. when disabled, all channels are switched off. functional block diagrams adg1233 s1b d1 s1a s2a in2 in1 in3 d2 s2b s3a d3 s3b switches shown for a logic 1 input 05743-001 logic en figure 1. switches shown for a logic 1 input 05743-038 ADG1234 s1b d1 s1a s2a in2in1 in3 d2 s2b s4b d4 s4a s3a d3 s3b logic en in4 figure 2. the i cmos (industrial-cmos) modular manufacturing process combines a high voltage complementary metal-oxide semi- conductor (cmos) and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no other generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased perfor- mance, dramatically lowered power consumption, and reduced package size. the ultralow capacitance and charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. i cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments. product highlights 1. 1.5 pf off capacitance (15 v supply). 2. 0.5 pc charge injection. 3. 3 v logic-compatible digital input, v ih = 2.0 v, v il = 0.8 v. 4. 16-lead tssop, 20-lead tssop, and 4 mm 4 mm lfcsp.
adg1233/ADG1234 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagrams............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dual supply ................................................................................... 3 single supply ................................................................................. 5 absolute maximum ratings ............................................................7 esd caution...................................................................................7 pin configurations and function descriptions ............................8 terminology .......................................................................................9 typical performance characteristics ........................................... 10 test circuits..................................................................................... 13 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 revision history 8/06rev. 0 to rev. a updated format..universal changes to table 1 ....3 changes to table 2 ....4 changes to figure 11..10 changes to figure 12..11 1/06revision 0: initial version
adg1233/ADG1234 rev. a | page 3 of 16 specifications dual supply v dd = +15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. y version 1 parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 120 typ v s = 10 v, i s = ?1 ma; see figure 24 190 230 260 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels (?r on ) 3.5 typ v s = 10 v, i s = ?1 ma 6 10 12 max on resistance flatness (r flat (on) ) 20 typ v s = ?5 v, 0 v, +5 v; i s = ?1 ma 60 72 79 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage i s (off ) 0.02 na typ v d = 10 v, v s = ?10 v; see figure 25 0.1 0.6 1 na max drain off leakage i d (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 25 0.1 0.6 1 na max channel on leakage i d, i s (on) 0.02 na typ v s = v d = 10 v; see figure 26 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 2 t transition 110 ns typ r l = 300 , c l = 35 pf 130 150 170 ns max v s = 10 v; see figure 27 t bbm 25 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = +10 v; see figure 28 t on (en ) 120 ns typ r l = 300 , c l = 35 pf 140 170 195 ns max v s = 10 v; see figure 29 t off (en ) 40 ns typ r l = 300 , c l = 35 pf 45 55 60 ns max v s = 10 v; see figure 29 charge injection 0.5 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 30 off isolation ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 31 channel-to-channel crosstalk ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 33 total harmonic distortion, thd + n 0.14 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz; see figure 34 ?3 db bandwidth 900 mhz typ r l = 50 , c l = 5 pf; see figure 32 c s (off ) 1.5 pf typ f = 1 mhz; v s = 0 v 1.7 pf max f = 1 mhz; v s = 0 v c d (off ) 1.6 pf typ f = 1 mhz; v s = 0 v 1.8 pf max f = 1 mhz; v s = 0 v c d , c s (on) 3.5 pf typ f = 1 mhz; v s = 0 v 4 pf max f = 1 mhz; v s = 0 v
adg1233/ADG1234 rev. a | page 4 of 16 y version 1 parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 260 a typ digital inputs = 5 v 420 a max i ss 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.002 a typ digital inputs = 5 v 1.0 a max v dd /v ss 5/16.5 v min/max gnd = 0 v 1 temperature range for the y version: ?40 c to +125c. 2 guaranteed by design, not subject to production test.
adg1233/ADG1234 rev. a | page 5 of 16 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. y version 1 parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance (r on ) 300 typ v s = 0 v to10 v, i s = ?1 ma; see figure 24 475 567 625 max v dd = 10.8 v, v ss = 0 v on resistance match between channels (?r on ) 5 typ v s = 0 v to10 v, i s = ?1 ma 16 26 27 max on resistance flatness (r flat (on) ) 60 typ v s = 3 v, 6 v, 9 v, i s = ?1 ma leakage currents v dd = 13.2 v source off leakage i s (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 25 0.1 0.6 1 na max drain off leakage i d (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 25 0.1 0.6 1 na max channel on leakage i d, i s (on) 0.02 na typ v s = v d = 1 v or 10 v, see figure 26 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ 0.1 a max v in = v inl or v inh digital input capacitance, c in 2 pf typ dynamic characteristics 2 t transition 135 ns typ r l = 300 , c l = 35 pf 170 200 230 v s = 8 v; see figure 27 t bbm 45 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 8 v; see figure 28 t on (en ) 150 ns typ r l = 300 , c l = 35 pf 195 230 265 v s = 8 v; see figure 29 t off (en ) 45 ns typ r l = 300 , c l = 35 pf 60 70 75 v s = 8 v; see figure 29 charge injection ?0.3 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 30 off isolation ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 31 channel-to-channel crosstalk ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 33 ?3 db bandwidth 600 mhz typ r l = 50 , c l = 5 pf; see figure 32 c s (off ) 1.5 pf typ f = 1 mhz; v s = 6 v 1.7 pf max f = 1 mhz; v s = 6 v c d (off ) 2 pf typ f = 1 mhz; v s = 6 v 2.2 pf max f = 1 mhz; v s = 6 v c d , c s (on) 4 pf typ f = 1 mhz; v s = 6 v 4.5 pf max f = 1 mhz; v s = 6 v
adg1233/ADG1234 rev. a | page 6 of 16 y version 1 parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = 13.2 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 260 a typ digital inputs = 5 v 440 a max v dd 5/16.5 v min/max v ss = 0 v, gnd = 0 v 1 temperature range for the y version: ?40 c to +125c 2 guaranteed by design, not subject to production test.
adg1233/ADG1234 rev. a | page 7 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog, digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d 24 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle mximum) 100 ma operating temperature range automotive temperature range (y version) C40c to +125c storage temperature range C65c to +150c junction temperature 150c tssop, ja , thermal impedance 112c/w lfcsp, ja , thermal impedance 30.4c/w reflow soldering peak temperature, pb-fee 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating is applied at any one time. 1 overvoltages at a, en , s, or d are clamped by internal diodes. current should be limited to the ma ximum ratings given. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg1233/ADG1234 rev. a | page 8 of 16 pin configurations and function descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 s1a d1 s1b s2a d2 s2b v dd in1 en v ss s3a in2 in3 d3 s3b gnd adg1233 top view (not to scale) 05743-002 figure 3. 16-lead tssop pin configuration 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 s1a d1 s1b s2b gnd v ss in1 s4a d4 s4b s3b en v dd in2 s2a d2 in3 s3a d3 in4 ADG1234 top view (not to scale) 05743-003 figure 4. 20-lead tssop pin configuration pin 1 indicator 1 d1 2 s1b 3 s2b 4 d2 11 v ss 12 en 10 s3b 9d3 5 s 2 a 6 i n 2 7 i n 3 8 s 3 a 1 5 v d d 1 6 s 1 a 1 4 g n d 1 3 i n 1 top view (not to scale) adg1233 05743-004 figure 5. 16-lead, 4 mm 4 mm lfcsp pin configuration, exposed pad tied to substrate, v ss pin 1 indicator 1 d1 2 s1b 3v ss 4 gnd 5 s2b 13 v dd 14 s4b 15 d4 12 s3b 11 d3 6 d 2 7 s 2 a 8 i n 2 1 0 s 3 a 9 i n 3 1 8 e n 1 9 i n 1 2 0 s 1 a 1 7 i n 4 1 6 s 4 a top view (not to scale) ADG1234 05743-005 figure 6. 20-lead, 4 mm 4 mm lfcsp pin configuration exposed pad tied to substrate, v ss table 4. 16-lead tssop/20-lead tssop pin configurations pin no. adg1233 16-lead tssop pin no. ADG1234 20-lead tssop mnemonic 1 16 v dd 2 2 s1a 3 3 d1 4 4 s1b 5 7 s2b 6 8 d2 7 9 s2a 8 10 in2 9 11 in3 10 12 s3a 11 13 d3 12 14 s3b 13 5 v ss 14 15 en 15 1 in1 16 6 gnd n/a 17 s4b n/a 18 d4 n/a 19 s4a n/a 20 in4 table 5. 16-lead lfcsp/20-lead lfcsp pin configurations pin no. adg1233 16-lead lfcsp pin no. ADG1234 20-lead lfcsp mnemonic 1 1 d1 2 2 s1b 3 5 s2b 4 6 d2 5 7 s2a 6 8 in2 7 9 in3 8 10 s3a 9 11 d3 10 12 s3b 11 3 v ss 12 18 en 13 19 in1 14 4 gnd 15 13 v dd 16 20 s1a n/a 14 s4b n/a 15 d4 n/a 16 s4a n/a 17 in4 table 6. adg1233/ADG1234 truth table en inx switch xa switch xb 1 x off off 0 0 off on 0 1 on off
adg1233/ADG1234 rev. a | page 9 of 16 terminology v dd most positive supply potential. v ss most negative power supply potential in dual supplies. in single-supply applications, it can be connected to ground. gnd ground (0 v) reference. r on ohmic resistance between d and s. r on difference between the r on of any two channels. i s (off) source leakage current when switch is off. i d (off) drain leakage current when switch is off. i d , i s (on) channel leakage current when switch is on. v d, v s analog voltage on terminal d, terminal s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on ( en ) delay time between the 50% and 90% points of the digital input and switch on condition. t off ( en ) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t bbm off time measured between the 80% point of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl , i inh input current of the digital input. i dd positive supply current. i ss negative supply current. off isolation a measure of an unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. bandwidth frequency at which the output is attenuated by 3 db. on response frequency response of the on switch. thd + n ratio of the harmonic amplitude plus noise of the signal to the fundamental.
adg1233/ADG1234 rev. a | page 10 of 16 8 typical performance characteristics source or drain voltage (v) on resistance ( ? ) 200 100 0 ?18 ?15 ?12 ?9 ?6 ?3 12 15 9 06 31 05743-031 180 160 140 120 80 60 40 20 t a = 25c v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v v dd = +13.5v v ss = ?13.5v figure 7. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ? ) 450 250 300 0 02 46 12 810 1 05743-033 4 400 350 150 200 100 50 t a = 25c v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v v dd = 10.8v v ss = 0v figure 8. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ? ) 450 250 300 0 02 46 12 810 1 05743-033 4 400 350 150 200 100 50 t a = 25c v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v v dd = 10.8v v ss = 0v figure 9. on resistance as a function of v d (v s ) for single supply temperature (c) on resistance ( ? ) 250 0 ?15 ?10 ?5 10 05 05743-034 15 150 200 100 50 t a = +25c t a = +85c t a = +125c t a = ?40c v dd = +15v v ss = ?15v figure 10. on resistance as a function of v d (v s ) for different temperatures, dual supply temperature (c) on resistance ( ? ) 600 0 024 10 68 05743-035 12 300 400 200 500 100 t a = +25c t a = +85c t a = +125c t a = ?40c v dd = 12v v ss = 0v figure 11. on resistance as a function of v d (v s ) for different temperatures, single supply temperature ( c) leakage current (pa) 250 ?250 ?200 ?150 ?100 ?50 0 100 50 150 200 0 20406080100120 05743-017 v dd = +15v v ss = ?15v v bias = +10v/?10v i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) ? ? i d , i s (on) + + i s (off) + ? figure 12. leakage currents as a function of temperature, dual supply
adg1233/ADG1234 rev. a | page 11 of 16 temperature (c) leakage current (pa) 130 ?120 ?70 ?20 30 80 0 20406080100120 05743-018 v dd = 12v v ss = 0v v bias = 1v/10v i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) ? ? i d , i s (on) + + i s (off) + ? figure 13. leakage currents as a function of temperature, single supply logic, in x (v) i dd (a) 200 60 80 100 120 140 160 180 40 20 0 0 2 4 6 8 10121416 05743-006 v dd = 12v v ss = 0v v dd = +15v v ss = ?15v i dd per channel t a = 25c figure 14. i dd vs. logic level v s (v) charge injection (pc) 6 4 2 0 ?2 ?4 ?6 ?15 ?10 ?5 0 15 10 5 05743-008 v dd = +15v v ss = ?15v v dd = 12v v ss = 0v v dd = +5v v ss = ?5v t a = 25c figure 15. charge injection vs. source voltage temperature ( c) time (ns) 220 180 200 160 140 120 100 80 20 40 60 0 ?40 ?20 200 40 60 80 100 120 05743-011 b off a on 15v ds b off a on 12v ds a off b on 12v ds a off b on 15v ds figure 16. t transition vs. temperature frequency (hz) off isolation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m 1g 05743-036 v dd = +15v v ss = ?15v t a = 25c figure 17. off isolation vs. frequency frequency (hz) crosstalk (db) ? 10 ?20 ?30 ?40 ?50 ?60 ?90 ?80 ?70 ?100 10k 100k 1m 10m 100m 1g 05743-012 sxa ? sxb s1x ? s2x v dd = +15v v ss = ?15v t a = 25c figure 18. crosstalk vs. frequency
adg1233/ADG1234 rev. a | page 12 of 16 frequency (hz) on response (db) 0 ?5 ?10 ?15 ?20 ?25 10k 100k 1m 10m 100m 10g 1g 05743-013 v dd = +15v v ss = ?15v t a = 25c figure 19. on response vs. frequency frequency (hz) thd + n (%) 10 1 0.10 0.01 10 100 1k 10k 100k 05743-037 load = 10k ? t a = 25c v dd = +5v, v ss = ?5v, v s = +3.5v rms v dd = +15v, v ss = ?15v, v s = +5v rms figure 20. thd + n vs. frequency v bias (v) capacitance (pf) 5.0 4.0 4.5 3.5 3.0 2.5 2.0 0.5 1.0 1.5 0 ?15 ?10 ?5 0 15 10 5 05743-010 source/drain on drain off source off v dd = +15v v ss = ?15v t a = 25c figure 21. capacitance vs. source voltage for dual supply v bias (v) capacitance (pf) 5.0 4.0 4.5 3.5 3.0 2.5 2.0 0.5 1.0 1.5 0 024 6 810 05743-009 12 source/drain on drain off source off v dd = 12v v ss = 0v t a = 25c figure 22. capacitance vs. source voltage for single supply v bias (v) capacitance (pf) 5.0 4.0 4.5 3.5 3.0 2.5 2.0 0.5 1.0 1.5 0 ?5 ?4 ?2?3 ?1 0 1 2 3 4 5 05743-007 source/drain on drain off source off v dd = +5v v ss = ?5v t a = 25c figure 23. capacitance vs. source voltage for dual supply
adg1233/ADG1234 rev. a | page 13 of 16 test circuits i ds sd v s 05743-020 v figure 24. on resistance sd v s a a v d i s (off) i d (off) 05743-021 figure 25. off leakage sd a v d i d (on) nc nc = no connect 05743-022 figure 26. on leakage 05743-023 inx v out d sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300 ? 50% 50% 90% 50% 50% 90% t on t off v in v out v in figure 27. switching timing 05743-024 inx v out d sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300 ? 80% t bbm t bbm v out v in figure 28. break-before-make delay
adg1233/ADG1234 rev. a | page 14 of 16 output 3v 0v 0v v o enable drive (v in ) 05743-025 en in3 in2 in1 s1b d1 v dd v ss v dd v ss gnd adg1233 r l 300? c l 35pf v s 50% 0.9v o 0.9v o t on (en) 50% v o s1a v in 0.1f 0.1f 50? t off (en) figure 29. enable delay, t on ( en ), t off ( en ) v in (normally closed switch) v out v in (normally open switch) off v out on q inj = c l v out 05743-026 inx v out d sxa v dd v ss v dd v ss gnd c l 1nf nc sxb v in v s 0.1f 0.1f figure 30. charge injection v out 50? network analyzer r l 50? inx v in sxa d v s v dd v ss 0.1f v dd 0.1f v ss gnd 05743-027 nc sxb off isolation = 20 log v out v s 50? figure 31. off isolation v out 50 ? network analyzer r l 50? inx v in sxa d v s v dd v ss 0.1f v dd 0.1f v ss gnd 05743-028 nc sxb insertion loss = 20 log v out with switch v out without switch figure 32. bandwidth channel-to-channel crosstalk = 20 log v out gnd sxa d sxb v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 05743-029 inx figure 33. channel-to-channel crosstalk v out r s audio precision r l 10 ? inx v in s d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 05743-030 figure 34. thd + noise
adg1233/ADG1234 rev. a | page 15 of 17 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 35. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 36. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters
adg1233/ADG1234 rev. a | page 16 of 16 compliant to jedec standards mo-220-vggc 2 . 2 5 2 . 1 0 s q 1 . 9 5 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicator top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 exposed pa d (bottom view) 12 max 1.00 0.85 0.80 seating plane 0.35 0.30 0.25 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.25 min 010606-0 0.75 0.60 0.50 figure 37. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-4) dimensions shown in millimeters 1 20 5 6 11 16 15 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicato r top view 3.75 bcs sq 4.00 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 pin 1 indicator figure 38. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-20-1) dimensions shown in millimeters ordering guide model temperature range package description package option adg1233yruz 1 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adg1233yruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adg1233ycpz-reel 1 ?40c to +125c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-4 adg1233ycpz-reel7 1 ?40c to +125c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-4 ADG1234yruz 1 ?40c to +125c 20-lead thin shrink small outline package (tssop) ru-20 ADG1234yruz-reel7 1 ?40c to +125c 20-lead thin shrink small outline package (tssop) ru-20 ADG1234ycpz-reel 1 ?40c to +125c 20-lead lead frame chip scale package (lfcsp_vq) cp-20-1 ADG1234ycpz-reel7 1 ?40c to +125c 20-lead lead frame chip scale package (lfcsp_vq) cp-20-1 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05743-0-8/06(a)

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